Thanks. Unfortunately, I think he's just speculating off the info in the datasheet like we are. That 1pF input capacitance is what the datasheet says - but that's the capacitance at the pin looking into the on-chip mux, not necessarily the value of the SAH capacitor.There's a some useful info here :
https://www.youtube.com/watch?v=TGjUHChO1kM
Well, being pedantic, you could derive CLK_SYS from the same source as CLK_ADC and so get cycle-precise timing, but the synchronisation logic that must exist in the chip makes it harder to work out what that precise timing might be (it's probably a fixed number of clock cycles delay, but measured from where is hard to guess).The ADC uses its own clock so you're unlikely to be able to get cycle accurate timing.
However, all we really want to know is a safe period after hitting START_ONCE before changing the input. I agree your guess at the operating sequence is quite a plausible one, but not the only possibility. The SAR certainly has to take 12 slots of some sort, but they could conceivably be 2-clock slots and a lot of time over for other stuff, or they could be 8-clock slots such that the SAR takes up the entire conversion time and everything else is pipelined (meaning that you don't get close to full speed unless operating in continuous mode).
So, in the absence of any official info, I think the only thing is to do some measuring. Other details of my target hardware makes this difficult to use for such measurements, but I think I'll start by measuring the throughput with START_ONCE vs START_MANY. And maybe a setup on a standard Pico (with an output GPIO driving an ADC) could allow measurement.
Statistics: Posted by arg001 — Tue Jan 30, 2024 10:48 am