Which version of the MIPI DSI spec are you reading that supports high speed reverse direction transfers?
V1.1 includes in section 5.2
HS reverse direction is documented in the D-PHY spec, but I haven't looked into which higher layer protocols allow it.
CSI2 clearly states that both data and clock lanes are unidirectional.
I don't believe that HS receive is supported in any way in the RP1 PHY (why would it when it's not supported by either CSI2 or DSI that use it?), but I know for certain that the software stack doesn't support it.
V1.1 includes in section 5.2
All the versions I have (up to 1.3.1) include the same wording.For bidirectional Lanes, data shall be transmitted in the peripheral-to-processor, or reverse, direction using Low-Power (LP) Mode only.
HS reverse direction is documented in the D-PHY spec, but I haven't looked into which higher layer protocols allow it.
CSI2 clearly states that both data and clock lanes are unidirectional.
I don't believe that HS receive is supported in any way in the RP1 PHY (why would it when it's not supported by either CSI2 or DSI that use it?), but I know for certain that the software stack doesn't support it.
Statistics: Posted by 6by9 — Tue Jul 16, 2024 12:08 pm